​You are cordially invited by the COE, to attend a Graduate Seminar, on the above given title, by Mr. Saif Ahmad, COE Part-Time Student, Department of Computer Engineering, on Saturday, 15th December, 2012, at  03:00 PM, in Building 24, Room 133.

Abstract: A recently developed low-cost method for speed characterization of ASICs' requires a portable on chip configurable clock generator to change and measure the frequency applied for characterization. The purpose of this work is to efficiently implement and evaluate the performance of a portable, digitally-controlled, all-digital, configurable clock generator using industry-standard advanced Electronic Design Automation (EDA) tools such as those from Synopsys, Mentor Graphics and Tanner EDA. Also, as a proof of concept, an ASIC chip, complete with circuits under test and test support circuitry including the portable clock generator is designed. An intensive analysis of single ended ring oscillators which represent the main building block of such configurable clock generators is provided. The evaluation of the ring oscillators is achieved by exploring existing digitally controlled oscillators and then most suitable one of them is determined for this project. In addition, the digitally controlled oscillator (DCO) is designed for an on-chip configurable clock generator for at-speed testing of ASICs, and is to have a minimum or standard cell size inverters and maximum possible frequency range with reasonable linear resolution. It is designed based on our theoretical analysis and verified by pre-layout and post-layout simulations in many process technologies. The DCO was sent for fabrication together with our configurable clock generator using TSMC 0.35U technology. A testing and on-chip supporting circuitry, to be serially connected with off-the chip specially developed test and characterization processor (TACP) to receive/send data from it and has the devices under test (DUTs), is designed and a complete ASIC design flow, from RTL to GDS-II, is accomplished and will be sent for fabrication using Foundry 150nm technology and Synopsys tools in late 2012.

Dr. Zubair Baig, Assistant Professor, COE Department, is his thesis advisor.​