ANNOUNCEMENT – CSE
DISSERTATION DEFENSE
Mr. Ayman
Hroub, Full-Time PhD Student (CSE), will
defend his PhD Dissertation on Wednesday, December 16, 2015
at 10:00 a.m. in 24-130. His PhD dissertation title is “A HYBRID
SOFTWARE/HARDWARE SIMULATION FRAMEWORK FOR EARLY ARCHITECTURAL EXPLORATION OF
CHIP MULTIPROCESSORS”. His dissertation advisor is “Dr. Muhammad
Elrabaa, Asso. Professor, COE Department”. You are
cordially invited to attend.
Abstract:
“Simulation
is the de facto tool for computer architecture performance evaluation. In the
multicore era, processors became much more complex. They comprise large number
of cores, complex memory hierarchies, and complex interconnection networks.
Thus, the design space to be explored became much larger. Moreover, this kind
of architectures has a voluminous number of concurrent events. Simulating these
events sequentially would be too slow. In the last few years, researchers
exploited the massive fine and coarse grained parallelism offered by FPGAs to
accelerate such simulations. This is done via building fine grained parallel
simulators such that the concurrent events of the simulated architecture are
mapped to the fine grained components of this simulator and hence simulated in
parallel. This approach has accelerated computer architecture simulation by
orders of magnitude. In this dissertation, we propose HySim, a trace-driven
hybrid software/hardware simulation framework for early architectural
exploration of chip multiprocessors. It exploits the flexibility of software
and the massive parallelism offered by the FPGAs. HySim is faster than
all existing simulators and in the same time its accuracy is in agreement with
the existing accurate simulators. Its speed is up to 2.2 GIPS with 14%
average absolute error relative to real hardware execution time. Since FPGAs
have limited storage resources and the multi-threaded applications have very
large execution traces, we have developed a technique to compress such traces.
This technique compresses the execution trace on-the-fly and stores it in an
executable format that can be interpreted by the timing simulator without a
need for a decompression phase. The proposed trace compression technique
achieved a compression ratio of up to 1862.20.”
Refreshment
will be served