COE 202
Digital Logic Design

Catalog Description

Introduction. Information processing, and representation, Numbering Systems, Binary codes, Boolean algebra, Manipulation and minimization of Boolean functions, Combinational circuits analysis and design, multiplexers, decoders and adders. Sequential circuit analysis and design, basic flip-flops, synchronous sequential circuits, registers, counters, timing sequences. ROM, PLA, PAL and FPGAs.

Prerequisite(s)

PHYS 102

Textbook(s) and/or other Required Material

Alan Marcovitz , “Introduction to Logic Design”, 3rd edition 2009, McGraw Hills.

Course Objectives

  • Use math and Boolean algebra in performing computations in various number systems and simplification of Boolean algebraic expressions,

  • Design efficient combinational logic circuit implementation from functional description.

  • Design simple sequential logic circuit implementations from functional description.

Topics Covered

  • Introduction. Information Processing, and representation. Digital vs. Analog quantities.

  • Weighted Number Systems. Decimal, Binary, Octal and Hexadecimal.

  • Arithmetic in Binary and Hex (addition, subtraction& Multiplication),

  • Number base conversion (Dec to Bin, Oct, and Hex).

  • BCD Codes: Excess-3 & other BCD codes, Parity Bits, Character Codes.

  • Binary logic and gates, Truth tables, Boolean Algebra, Basic identities. Principle of duality.

  • DeMorgan’ Theorem.

  • Manipulation of Boolean expressions.

  • Gate Implementation of Boolean expressions

  • Canonical and Standard forms, Minterms, Maxterms, Sum of products & Products of Sums.

  • 2-Level gate implementation (SOP, POS, AOI, OAI), and multi-level logic.

  • From Truth tables to Boolean Expressions.

  • Physical properties of gates: fan-in, fan-out, propagation delay. Timing diagrams. Tristate drivers.

  • Map method of simplification: 2, 3 and 4-variable maps. Implicants, Prime Implicants, Essential Prime Implicants.

  • POS simplification.

  • Don’t care conditions and simplification.

  • Universal gates (NAND, NOR)

  • Implementation usingNand and NOR gates: 2-level & Multilevel implementation.

  • Exclusive-OR (XOR) and Equivalence (XNOR) gates, Odd and Even Functions, Parity generation and checking.

  • Combinational Circuit Design Procedure & Examples.

  • Code Converter.

  • BCD to 7-Segment Display Conversion.

  • Half and Full Adders.

  • Ripple Carry Adder design and Delay analysis of RCA.

  • Signed Numbers: sign-magnitude, 1`s complement, and 2`s complement.

  • Signed Binary Arithmetic. (Addition and Subtraction).

  • Binary Adder-Subtractor.

  • Carry Look-ahead adder.

  • Delay analysis.

  • Decoders 2x4, 3x8, 4x16. Designing large decoders from smaller decoders. Function implementation using decoders.

  • Encoders: Priority Encoders.

  • Multiplexers: 2x1, 4x1. Constructing large MUXs from smaller ones.

  • Function implementation using multiplexers.

  • Magnitude Comparator.

  • MSI Design Examples.

  • Sequential Circuits: Latches, Clocked latches: SR, D, T and JK. Race problem in clocked JK-Latch.

  • Flip-Flops: Master-Slave, D-FF.

  • Using D-FF to build other flip-flops.

  • Asynchronous/Direct Clear and Set Inputs. Setup, Hold, FF propagation delay.

  • Sequential Circuit Design. Design procedure, State diagrams and state tables.

  • Analysis of Sequential Circuits. State table, State diagram.

  • Registers, Registers with parallel load.

  • Synchronous Binary Counters: Up-Down Counters.

  • Counters with Parallel load, enable, synchronous clear and asynchronous clear.

  • Use of available counters to build counters of different count.

  • Design with unused States.

  • Shift Registers. Bi-directional shift register.

  • Mealy vs. Moore machine.

  • Design Examples and Calculation of maximum clock frequency.

  • Memory devices: RAMs &ROMs .

  • Combinational Circuit Implementation with ROM.

  • Sequential Circuit Implementation using ROMs.

  • Programmable Logic Devices: PLAs, PALs, FPGA'a.

  • Review.

Prepared by: Dr. Alaaeldin Amin, February 24, 2014.