Introduction to computer organization, machine instructions, addressing modes, assembly language programming, integer and floating-point arithmetic, CPU performance and metrics, non-pipelined and pipelined processor design, datapath and control unit, pipeline hazards, memory system and cache memory.

COE 200 and ICS 201

Computer Organization & Design: The Hardware/Software Interface, 4th edition, David A. Patterson and John L. Hennessy, Morgan Kaufmann, 2009.

• Describe the instruction set architecture of a MIPS processor
• Analyze, write, and test MIPS assembly programs
• Describe organization and operation of integer and floating-point arithmetic units
• Design the datapath and control of a single-cycle (non-pipelined) CPU
• Design the datapath and control of a pipelined CPU and handle hazards
• Describe the organization and operation of memory and caches
• Analyze the performance of processors and caches.

• Introduction to computer organization, high-level, assembly, and machine languages, components of a computer system, processor datapath, control, memory hierarchy, disk storage, technology improvements, chip manufacturing process.
• Review of signed/unsigned integers, binary addition and subtraction, carry and overflow. Instruction set architecture, registers, instruction formats, arithmetic instructions, immediate operands, bit manipulation.
• Load and store instructions, flow control instructions, pseudo-instructions, and addressing modes.Translating expressions, if-else statements, loops, array indexing and traversal.
• MIPS assembly language programming, tools, program template, directives, text, data, and stack segments, defining data, arrays, and strings, symbol table, memory alignment, byte ordering, and console input and output.
• Defining procedures, procedure calls and return address, nested procedure calls, passing arguments in registers, runtime stack, stack frames, local variables, value and reference parameters, saving and restoring registers.
• Integer multiplication, unsigned and signed multiplication, sequential multiplier hardware, faster (tree) hardware multiplier, integer division, sequential divide hardware, integer multiplication and division in MIPS.
• Floating point representation, IEEE 754 standard, normalized and de-normalized numbers, zero, infinity, NaN, FP comparison, FP addition, FP multiplication, rounding and accurate arithmetic. Floating-point instructions.
• CPU performance and metrics, CPI, performance equation, MIPS as a metric, Amdahl's law, benchmarks and performance of recent processors.
• Designing a processor, register transfer level, datapath components, clocking methodology, singlecycle datapath, implementing a register file and multifunction ALU.Control signals and control unit, ALU control.
• Pipelining versus serial execution, MIPS 5-stage pipeline, pipelined datapath, pipelined control, pipeline performance.Pipeline hazards: structural, data, and control hazards, load delay, hazard detection, stall and forwarding unit, and delayed branching.
• Main memory organization and performance, SRAM, DRAM, latency and bandwidth, memory
  hierarchy, cache memory, locality of reference.Cache memory organization: direct-mapped, fullyassociative, and set-associative caches, write policy, and replacement policy.Cache performance, memory stall cycles, and average memory access time.

Prepared by: Dr. Mayez Al-Mouhamed, March 7, 2014.