Catalog Description

Review of sequential circuits design and analysis, Data path and control unit design, Design with Hardware Description languages (HDL), Design with Field-Programmable Gate Arrays (FPGAs), Block interfacing, and high-level-synthesis.

Prerequisite(s)

COE 202 Digital Logic Design

M. D. Ciletti, "Advanced Digital Design with the Verilog HDL," (Prentice Hall), 2/e, 2010.

Introduce students to the design methodologies of digital systems with special emphasis on FPGA implementations.

• Introduction to Digital Design Methodology. Review of combinational logic design. Review of Sequential circuit design, Mealy versus Moore Machines, timing constraints, State minimization, State assignment.
• Design of a digital system by partitioning it into a Data Path and Control unit -- Design of DP and CU. Algorithmic State Machine (ASM) charts.
• Introduction to logic design with Verilog: structural models of combinational logic, logic system, design verification and test methodology, propagation delay, truth table models of combinational and sequential logic with Verilog. Logic design with
  behavioral models of combinational and sequential logic: continuous assignment models, dataflow/RTL models, algorithmic based models.
• Synthesis of combinational and sequential logic: Introduction to synthesis, synthesis of combinational logic, synthesis of sequential logic, high-level synthesis, synthesis of three-state devices and bus interfaces, synthesis of explicit state machines, synthesis of implicit state machines, synthesis of loops. Design and synthesis of Datapath controllers. Block interfacing.
• Field Programmable Gate Arrays (FPGAs), FPGA technologies, Verilog based design flows for FPGAs, design and synthesis with FPGAs.

Prepared by: Dr. Aiman El-Maleh, March 1, 2014.