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I. Written Part of the Comprehensive Exam (CompExam)
- The CompExam shall test the candidate’s fundamental knowledge in COE/ICS. It shall also test the academic maturity of the candidate to pursue a PhD degree.
- The CompExam shall be offered once a year, on Thursday of the first week of classes of the spring semester[1].
The student shall register for the exam by the end of the tenth week of the preceding semester.
- The CompExam shall be managed and administered by the Joint Program Committee.
- The CompExam shall cover the following five areas:
- Area #1: Computer Architecture and Parallel Processing
- Area #2: Digital System Design and Automation
- Area #3: Computer Networks
- Area #4: Operating Systems
- Area #5: Computer Algorithms
- The CompExam is a closed book exam and shall last for four hours.
The CompExam booklet shall consist of five separate exam papers, each representing a single area of
concentration listed in item 5. Each exam paper is a one-hour exam in length with a total of 100 points.
The candidate shall choose only four exam papers to answer.
- The examination shall be considered “FAIL” if the sum of the total scores of the four areas is less than 280.
Otherwise, the examination is considered “PASS”
- A candidate who fails the CompExam shall re-attempt it only once in its next administration.
A second failure will require the candidate to withdraw from the program.
II. Oral Part of the Comprehensive Exam
More to come later on the Oral Part.
Topics, Relevant Courses and Suggested References
I. Computer Architecture and Parallel Processing
Topics
1. Instruction set architectures design
2. Instruction pipelining, advanced ILP, and performance
3. Hierarchical memory system, cache memory, performance and design tradeoffs
4. Storage Systems
5. Parallel architectures: distributed memory multicomputers, shared memory multiprocessors, cache coherence and memory consistency protocols, interconnection networks, and performance.
Books
1. Hennessey & Patterson, Computer Architecture: A Quantitative Approach, third edition.
2. Culler and Singh, Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann.
Courses
COE501, COE502
II. Digital Design & Automation:
Topics
1. Combinational logic: Boolean algebra, Canonical forms, Karnaugh maps, logic minimization, Decoders, encoders, multiplexers, comparators, PLA’s.
2. Sequential logic: Latches & flip-flops, setup and hold times and timing diagrams, design procedure, state diagrams,
state tables and state minimization. Mealy vs. Moore models of FSMs. Registers, counters, RAMs, ROMs, PLDs, and FPGAs. RTL level design, pseudo HDL description, data and control path design
3. VLSI Design: Design of basic CMOS logic (Static, dynamic and PTL). ASIC design methodologies (custom vs. semi-custom). ASIC design flow (Design entry, logic synthesis, technology mapping, placement, and routing).
4. Computer arithmetic: High speed and Carry-Save adders. Design of sequential multipliers: Booth and modified Booth algorithms. Array and tree multipliers: Wallace tree, Dadda and Baugh Wooley. Floating point representation.
5. Hardware synthesis & Design Automation: Combinatorial optimization (shortest & longest path problems,
graph coloring, clique covering and partitioning, Linear programming and max-min flow. Binary decision diagrams (BDDs). Hardware modeling (HDLs and dataflow). Architecture synthesis (Data path synthesis, and control synthesis). Scheduling and binding algorithms.
Books:
1. Morris Mano and Charles Kime, Logic and Computer Design Fundamentals, Second Edition, Prentice Hall International, 2000.
2. Israel Koren, Computer Arithmetic algorithms, second edition, A. K. Peters Ltd. 2002
3. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison Wesley, 1993.
4. Giovani De Michelli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.
5. Christos H. Papadimitriou and Keith Steiglitz, Combinatorial Optimization – Algorithms & Complexity, Prentice Hall
Courses:
COE 360, COE 561, COE 586
III. Computer Networks
Topics
1. Computer networking concepts, basic terminology, protocols, communication architectures, and OSI reference model
2. Data link layer, ARQ strategies, analysis of ARQ strategies, multi-access communication and protocols
3. ATM
4. Delay models in data networks
5. Introduction to performance analysis and queuing networks
6. Little's theorem
7. Single server queuing models and network of queues
8. Network layer, routing, flow control, congestion control, protocols
9. Transport and application layers and protocols
Books
1. Computer Networking: A Top-Down Approach Featuring the Internet by Kurose and Ross, Addison Wesley, 2003.
2. Data Networks by Dimitri Bertsekas and Robert Gallager, Prentice Hall, 1992.
3. Computer Networks by Andrew Tanenbaum, Prentice Hall, 1996.
Courses:
COE540 or ICS 570
IV. Operating Systems
Topics:
1. Processes, Threads, SMP, and Microkernels
2. Synchronization of processes and threads
3. Uniprocessor and Multiprocessor scheduling
4. Real-Time Systems and Scheduling
5. Memory Management and Virtual Memory
6. I/O Management, disk scheduling, RAID
7. File Management
8. Distributed File Systems
Books:
1. William Stallings , Operating Systems, Fourth Ed. 2001, Prentice Hall, Inc.
2. Siblerschatz and Galvin, Operating System Concepts 6th Ed. 2002 Addison Wesley, Inc.
Courses
ICS 531
V. Computer Algorithms
Topics:
1. Divide and conquer.
2. Dynamic programming.
3. Computational Geometry: Covex hull, Nearest neighbors, Voronoi diagrams.
4. NP-complete problems.
5. Network flow.
6. Matching.
7. Approximation algorithms.
8. Randomized algorithms.
Books:
1. Alsuwaiyel, M. H., Algorithms: Design Techniques and Analysis, World Scientific Publishers, 1999.
2. Cormen, T. H., Leiserson, C. E. and Rivest, R. L. Introduction to Algorithms, MIT Press, Cambridge, 1992.
Courses
ICS 353, ICS 553
[1] As an exception for the Academic year 2003-2004, the exam shall be offered on Thursday of the first week of classes of the fall of 2004, in addition to the regular exam.
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