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 CSE 671: Silicon Compilation And High-Level Synthesis

​Course Information

Designation:   Required Course

Course Level:   Graduate


Prerequisite(s) by Topic: 

COE 542 or Consent of the Instructor

Catalog Description: 

Levels of abstraction: behavioral, structural, and physical levels. Design description. Module generation (functional cell generation, gate matrix layout, PLAs, etc.) and Module optimization. High level synthesis: Intermediate forms (data flow and control flow graphs), Scheduling algorithms, data flow and control flow synthesis, resource allocation, and module binding. Knowledge based and expert system approach to Design Automation.​