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Modern Digital System Design using VHDL:
College of Computer Sciences & Engineering Computer Engineering
This course is a good practical introduction to modern techniques for digital system design, modeling, automated synthesis, and performance evaluation. The VHDL hardware description language adopted as a standard by the IEEE in 1987 (IEEE standard 1076-1987) is used as a major tool to illustrate these techniques. The course is complemented with a well designed set of hands on laboratory exercises and case studies to further stress various aspects of digital system design. VHDL main language constructs and various modeling strategies will be studied. Behavioral, structural, and dataflow representations of digital systems are reviewed. Advanced language features, e.g. accurate timing models, constraint checking, data abstraction, signal resolution, external interfaces, libraries and packages will be covered. In addition, the course will explore alternative VHDL coding styles that will synthesize into more efficient hardware. Mismatches between pre-synthesis simulation and post-synthesis hardware simulation will be highlighted.
The course is intended for engineers involved in digital system design, modeling, analysis and performance evaluation.
Changes may take place on scheduling of short courses without any prior notice.
To be sure, please contact at: KFUPM Box 5026, Dhahran 31261
Telephone 03 860-1234 E-Mail cont-edu@kfupm.edu.sa |
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