Sign In
 

 Topics for PhD Comprehensive Examination

Area 1: Computer Architecture and High-Performance Computing

Topics:

  1. Fundamentals: technology trends, cost, power, dependability, performance.
  2. Instruction Level Parallelism: dynamic scheduling, speculation, hazards, dynamic branch prediction, multiple issue, static scheduling and VLIW, compiler techniques for exposing ILP, loop unrolling, and software pipelining.
  3. Memory Hierarchy: cache memory, hardware/software techniques to improve cache performance, virtual memory, performance, and design tradeoffs.
  4. Multiprocessor and Thread-Level Parallelism: symmetric multiprocessors, snooping coherence protocols, distributed shared memory, directory-based coherence, synchronization.
  5. Basic parallel programming techniques, decomposition, assignment, orchestration, and mapping. Performance: evaluation, scalability, and workload selection.

Books:

1.      Hennessey & Patterson, Computer Architecture: A Quantitative Approach, latest edition.

2.      Culler and Singh, Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann, latest edition.

Area 2: Computer Networks

Application Layer: Principles of Network Applications, The Web and HTTP, File Transfer: FTP, Electronic Mail in the Internet, DNS—The Internet's Directory Service, Peer-to-Peer Applications

Transport Layer: Connectionless Transport: UDP, Principles of Reliable Data Transfer, Connection-Oriented Transport: TCP, Principles of Congestion Control, TCP Congestion Control

Network Layer: Virtual Circuit and Datagram Networks, The Internet Protocol (IP), Addressing and Subnetting, Routing Algorithms, Internet Routing Protocols, Spanning Tree Algorithms, Principles of Mobility Management and Mobile IP

Link Layer and Local Area Networks: Services and Multiple Access Protocols, ARQ strategies, analysis of ARQ strategies, Ethernet: 802.3, Wi-Fi: 802.11 Wireless LANs

Delay Models in Data Networks {ref 2: chapter 12]

Little's theorem, Single and multiple servers queuing models, Network of queues (Jackson's theorem)

Network Security: Cryptography: Principles, Ciphers, Diffie-Hellman Key Exchange, DES, AES, Cipher Modes; Public Key Infrastructures: RSA, Public Key Certificates, X.509; Digital Signatures: Message Digests, Symmetric Key Signatures, Public Key Signatures, Attacks; Security Protocols: Kerberos, SSL/TLS, IPSEC. 

References: 

[1] Computer Networks by Andrew Tanenbaum, Prentice Hall; 5 edition, 2010.

[2] Probability, Statistics, and Random Processes for Electrical Engineering by L. Garcia, Prentice Hall; 3rd edition, 2008.

Area 3: Computer Networks Security

Cryptography: Principles, Ciphers, Diffie-Hellman Key Exchange, DES, AES, Cipher Modes;

Public Key Infrastructures: RSA, Public Key Certificates, X.509; Digital Signatures: Message Digests, Symmetric Key Signatures, Public Key Signatures, Attacks;

Security Protocols: Kerberos, SSL/TLS, IPSEC, Hash Functions, and Other Topics, Access Control, Authentication, Authorization, Simple Authentication, Real-World Security Protocols

Security attacks: Side-Channel Attacks, Cache Attacks on Ciphers

References:

Information Security: Principles and Practice, Mark Stamp, Wiley, 2nd Edition, 2011.

Area 4: Digital System Design and Automation Area

Topics:

  1. Fundamentals of Digital System Design: Combinational & Sequential logic. Moore and Mealy Machines, Data Path and control unit design. Understanding of ASIC design flow (Design entry, logic synthesis, technology mapping, placement, and routing). Design merits; complexity, area, speed, and power dissipation.
  2. Hardware modeling and hardware description language: Design Hierarchy, and design partitioning & Top-Down Design. Modeling constructs. Structural, behavioral and RTL Models, Modeling Iterative/Regular Structures, and Test Benches. Design Organization & Parameterization.  HDL coding for synthesis.
  3. High-Level Synthesis: data flow and control sequencing graphs, data-flow based transformations, Architectural Synthesis, resources and constraints, scheduling, time-constrained scheduling, resource-constrained scheduling, heuristic scheduling algorithms: List scheduling, Allocation, and Binding: resource sharing, register sharing. Data path and control unit synthesis.

References:

  1. M. D. Ciletti, "Advanced Digital Design with the Verilog HDL," (Prentice Hall), 2/e 2010.
  2. Synthesis and Optimization of Digital Circuits – Giovanni De Micheli, McGraw Hill International Edition, ISBN –0-07-113271-6, 1994. (Chapters 4-6).

303